1. Field of the Invention
The present invention generally relates to a jitter measurement circuit, in particular, to a built-in clock jitter measurement circuit.
2. Description of Related Art
When a data pulse is transmitted on a transmission line, problem may be caused in a clock recovery circuit (CDR) or a phase lock loop (PLL) or the data may even be lost if a data jitter appears. Jitter is a deviation between the real timing and the ideal timing of rising edges (or falling edges) of a signal. FIG. 1 illustrates the definition of jitter. Jitter may negatively affect bit error rates (BER) of receivers and reduce the quality of service of systems.
Generally speaking, jitter appears as two distinct types: deterministic jitter (DJ) and random jitter (RJ). RJ usually presents a Gaussian distribution, or referred as normal distribution.
Presently, an external automatic test equipment (ATE) may be used for measuring jitter. However, since signals have to be output to the ATE, they have to go through the input/output pins. Thus, the measured jitter may not be original. Besides, high cost of ATEs increases testing cost.
Accordingly, a built-in self-test (BIST) circuit capable of performing accurate jitter measurement is to be developed for reducing testing cost, testing time, and prevent usage of external test equipment.